The present invention relates to PWM modulation and more specifically to a method and apparatus for increasing voltage resolution across a generator exciter field coil where the exciter voltage is determined by a counter that is less precise than a desired voltage resolution.
Pulse width modulation (PWM) hardware configurations and control algorithms are used in many different control applications. One particularly advantageous use of PWM techniques is in controlling generator terminal voltage by varying the voltage across a generator exciter coil. To this end, three-phase AC voltage is fed back from a generator output to an AC to DC rectifier that generates DC voltage across a DC bus link. Typical generator controlling PWM hardware includes an IGBT switch linked between the DC link and the exciter coil. The switch is opened and closed to provide essentially square wave PWM voltage pulses on the line linked to the coil. The width or duration of a voltage pulse divided by a full PWM cycle period is referred to generally as a PWM pulse duty cycle.
Each xe2x80x9conxe2x80x9d part of the voltage pulse causes the current through the exciter coil to increase while the xe2x80x9coffxe2x80x9d part of the pulse causes the current through the exciter coil to decrease. Because the exciter coil consists of a large inductance even after a voltage pulse occurs, the coil continues to draw current as a result of the pulse. For this reason, at any given time the current magnitude is a function of the residual current level at the beginning of the most recent voltage pulse, the duration of the most recent voltage pulse and the period since the most recent voltage pulse. In other words, the current is an integration of temporally proximate previous voltage pulses.
A typical controller for controlling a PWM switch receives an input signal indicating a desired generator terminal voltage and provides output signals to open and close the PWM switch such that the pulse duty cycle causes the desired exciter current. To this end many controllers are equipped with a counter that, based on the desired exciter voltage, adjusts pulse duty cycle by increasing or decreasing the counts corresponding to pulse duty cycles. For example, to increase exciter current, switch on time may be increased from 100 count per PWM cycle to 150 count per PWM cycle.
Where exciter current is based on counter value and a simple counter control algorithm is adopted, exciter current resolution is limited by the maximum counter value. For example, where the maximum counter value is 255, exciter current resolution is one part in 256 (i.e., only 256 different voltage duty cycle durations can be achieved). While such limited resolution may be acceptable in some control applications, such resolution is not acceptable in many other applications and therefore a need exists to increase exciter winding current resolution.
One solution to increase duty cycle resolution is to increase the counter size. Unfortunately, while possible, this solution is impractical in existing systems that employ a relatively low maximum value counter. In addition, the costs associated with redesigning existing controller configurations to accommodate a higher maximum value counter would be excessive.
Another solution to increasing the effective resolution of the exciter duty cycle has been to provide sequences of voltage pulses that together, over a short period, generate a relatively higher resolution average coil voltage. In this regard it has been recognized that, because the exciter coil is inductive and hence instantaneous current is generally a current integration caused by temporally proximate voltage pulses, the instantaneous effective voltage across the coil can be adjusted to between first and second resolutions by causing consecutive voltage pulses at first and second duty cycles corresponding to the first and second resolutions, respectively. For example, to achieve a resolution corresponding to a count 175.5, the controller controls the duty cycle to generate consecutive voltage pulses having 175 and 176 counts, respectively (i.e., (175+176)/2=175.5). Similarly, according to a technique referred to as a xe2x80x9cfraction of fourxe2x80x9d approach, to achieve a resolution of 125.25, the controller controls the duty cycle to generate consecutive voltage pulses having 126, 125, 125 and 125 counts, respectively.
While the fraction of four and other similar techniques achieve fractional duty cycle resolution, these techniques also have shortcomings. In particular, these techniques result in the appearance of limit cycles in the generator terminal voltage. The limit cycles were caused by the control algorithm cycling through a discrete number of states in an attempt to hold the output voltage to a regulation set point and appear as a complex, somewhat sinusoidal oscillation of the generator output RMS voltage. Limit cycle oscillations are unacceptable in many electric power applications.
Thus, there is a need for a method and/or apparatus that can be employed with existing controllers that employ relatively low maximum value counters to increase voltage resolution without causing limit cycles.
According to the present invention voltage resolution limitations associated with small bit register counters can be overcome while limiting or essentially eliminating the effects of limit cycles using several related control techniques. To this end, when a requested duty cycle is received that has a higher resolution than a register counter, first and second consecutive counts supported by the register counter and corresponding to a lower duty cycle level and an upper duty cycle below and above the requested higher resolution duty cycle, respectively, are identified. Then, over a specific number D of PWM cycles, the first and second counts are selected in a random fashion to form a ratio that is proportional to the difference between the required duty cycle and the lower duty cycle divided by the difference between the upper duty cycle count and the lower duty cycle count. A selected count is provided to the PWM register counter every PWM cycle and is used during the corresponding cycle to generate a PWM pulse having a duration corresponding to the selected count.
In one embodiment, the received requested signal S is within a count range 0 through Y where the voltage value corresponding to count Y is essentially equal to the voltage value corresponding to a maximum register count X and where count Y is greater than count X. For example, maximum counter X may be 255 while maximum request signal value Y maybe 32,767and each of X (e.g., 255) and Y (e.g., 32,767) may correspond to 20 volts. In this case, count 128 on the X scale would equal count 16,384 on the Y scale and each would correspond to 10 volts. In this case, the step of identifying the first count includes dividing the request signal S by the value D to obtain the first count and a remainder R where value D is essentially equal to Y/X (i.e., is equal to the integer portion of Y/X) and the step of identifying the second count includes incrementing the first count. In the present example where Y is 32,767 and X is 255, D is 128.
In one embodiment the step of randomly selecting a PWM count increment includes identifying a random number of N within the range 0 through Dxe2x88x921, comparing the remainder R and number N and, if the random number N is less than remainder R, selecting the second count, else selecting the first count and, over each D PWM cycles, identifying each of 0 through Dxe2x88x921 only once. In one embodiment the step of identifying includes identifying random numbers in different orders during consecutive D PWM cycles.
Thus, one object of the invention is to minimize or eliminate limit cycling. By randomly selecting between the first and second counts instead of selecting the counts in a specific pattern, the periodicity of the selection is randomized and limit cycling is essentially eliminated.
Another object is to provide high resolution voltage levels using a relatively low bit register counter. Resolution between second to first voltage levels is accomplished by controlling the ratio of first and second counts over consecutive PWM cycles where the first and second counts correspond to the first and second voltage levels. The second and first counts are selected in a ratio proportional to the difference between the requested voltage level and the first voltage level divided by the difference between the first and second voltage levels. The ratio is facilitated by providing each random number 0 through Dxe2x88x921 only once during each D PWM cycles.
In another embodiment where the maximum requested signal count Y is at least 8xc3x97xe2x88x921 the random numbers may be selected using a repeating pseudo-random number generator. As the nomenclature implies, a repeating pseudo-random number generator repeats a number sequence periodically. For example, where the generator generates numbers in the 0-127 range, every 128 PWM cycles the number generator repeats the number sequence. It has been recognized that, while using a pseudo-random number generator to generate repeating random number sequences still causes some limit cycling, where the maximum request signal count Y is relatively large (e.g., 8xc3x97xe2x88x921) limit cycling is appreciably reduced and the minimal cycling that remains is acceptable for many applications.
Other processes for generating random numbers are contemplated including using a lookup table, generating a Z-bit random number and scaling the Z-bit number to within the range 0 through Dxe2x88x921, providing a seed number to a congruential number generator.
These and other objects, advantages and aspects of the invention will become apparent from the following description. In the description, reference is made to the accompanying drawings which form a part hereof, and in which there is shown a preferred embodiment of the invention. Such embodiment does not necessarily represent the full scope of the invention and reference is made therefore, to the claims herein for interpreting the scope of the invention.